The 16th annual workshop on Microprocessor Test and Verification will be held in Austin, TX on Dec 3-4, 2014.
The full two-day program will take place from 8 AM to 6 PM on Dec 3 and 4 and it will feature invited talks by verification experts, technical paper sessions, three panels and many special invited sessions on various hot topics. To encourage and promote technical exchange among the attendees, various social activities are planned during the two days including continental breakfast and lunches on both days as well as a very lavish dinner on the evening of Dec 3 at Fogo De Chao Brazilian restaurant in downtown Austin.
On Dec 2 before MTV starts, MTV attendees are also encouraged to attend a lunch organized by the Design Verification (DV) Club of Austin at the Norris Conference center in North Austin featuring several speakers and tutorial presenters.
A detailed advanced program for all activities associated with MTV will be available soon.
The purpose of MTV is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This is the 15th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross- examination of test and verification experiences and innovative solutions.
Areas of Interest include
- Validation of microprocessors and SOCs
- Experiences on test and verification of high performance processors and SOCs
- Test/verification of multimedia processors and SOCs
- Performance testing
- High-level test generation for functional verification
- Emulation techniques
- Silicon debugging
- Low Power verification
- Formal techniques and their applications
- Verification coverage
- Test generation at the transistor level
- Equivalence checking of custom circuits at the transistor level
- ESL Methodology
- Virtual Platforms
- Software verification
- Circuit level verification
- Switch-level circuit modeling
- Timing verification techniques
- Path analysis for verification or test
- Design error models
- Design error diagnosis
- Design for testability or verifiability
- SAT for testing and formal verification
- Security Verification